Conventional fractional-N frequency synthesizers achieve average non-integer division ratio by modulating a loop frequency divider's dividing ratio. In order to suppress quantization noise, a finite impulse response filter (FIR) with a specific frequency response is introduced into the fractional-N frequency synthesizer' loop, and forms a structure including the FIR filter and components such as in a conventional phase locked loop (PLL). By controlling the frequency response of the FIR filter, suppression of quantization noise in a specific frequency range can be achieved, which improves the performance of the frequency synthesizer.
Conventionally, a FIR filter based quantization noise filter needs a multi-path frequency divider in a frequency synthesizer. Since the loop frequency dividers receive the output of a voltage controlled oscillator (VCO) (in most cases, the VCO frequency is the highest frequency of the frequency synthesizer), multi-path realization inevitably increases power consumption. Further, for the design of a frequency synthesizer including analog modules, multi-path causes increased areas, which also poses a problem since it takes up valuable silicon area on a chip. In addition, due to compact placement of multi-path, the coupling among the frequency dividers will add time errors to each output path, which will further affect the overall performance. Therefore, it may be desirable to design a circuit that improves the performance.